Tony Funderburk is Director of Global Electronics & High Tech PLM Sales at PTC, where provides guidance and support for companies looking to accelerate innovation, manage product complexity, and drive digital transformation through Product Lifecycle Management (PLM) solutions. With more than 25 years of experience in enterprise software sales and leadership, Tony brings deep expertise across the electronics and semiconductor industries, working closely with organizations to improve product development, strengthen collaboration, and build more resilient operations.
TL;DR: Advanced packaging—from chiplets to 2.5D/3D stacking—has transformed the package from a commodity enclosure into a core product differentiator. When the package becomes part of the product architecture, every design decision carries lifecycle consequences. Teams that treat packaging as a lifecycle-managed engineering discipline gain speed, quality, and competitive edge.
The performance era defined by Moore's law is giving way to a new one—defined by how well companies can architect, integrate, and manage what happens inside the package. Chiplets, 2.5D interposers, 3D stacking, and fan-out wafer-level packaging are no longer advanced options reserved for a handful of leading-edge manufacturers. They are rapidly becoming the standard approach for anyone competing in AI, high-performance computing, automotive, and 5G.
The implication for engineering organizations is significant. A package that once held a chip now is the chip architecture. And managing it requires a fundamentally different approach—not just to design, but to the entire product lifecycle.
Advanced packaging is one of the clearest examples of why semiconductor complexity is outpacing traditional engineering processes.
Why has advanced packaging become a key competitive differentiator?
The numbers make the case plainly. The advanced packaging market was valued at approximately $45 billion in 2024 and is forecast to grow at a 9.4% CAGR, reaching roughly $80 billion by 2030. High-end performance packaging—the segment built around chiplet integration—is growing even faster, at a projected CAGR of 23% between 2024 and 2030, reaching an estimated $28.5 billion. TSMC, Samsung, and Intel are leading 2025 capital expenditure in advanced packaging, a signal that packaging is now a primary axis of competition, not a commodity afterthought.
The reason is straightforward: transistor scaling alone can no longer deliver the performance gains that AI workloads and high-bandwidth applications demand. Chiplet-based designs allow companies to mix and match dies optimized for different process nodes—combining, for example, a high-performance logic die with a memory die and an analog I/O die in a single package. By breaking large, complex systems into smaller functional dies, chiplet architectures can help reduce development complexity, improve manufacturability, and increase yield compared with equivalent monolithic designs.
That makes advanced packaging not just a way to extend performance, but a practical strategy for managing cost, risk, and scalability as semiconductor architectures become more complex.
These are not incremental gains. They represent a structural shift in how semiconductor performance is achieved and who achieves it.
How does advanced package complexity strain engineering teams?
Packaging has always involved multiple disciplines. But the shift to heterogeneous integration changes the nature of cross-disciplinary collaboration in ways that most engineering organizations are not yet structured to handle.
What makes heterogeneous integration disruptive to traditional design methods?
Heterogeneous integration requires engineering teams to move beyond traditional, sequential design methods. Instead of optimizing individual components in isolation, teams must optimize the full package as an interconnected system—coordinating silicon, substrate, interposer, thermal, mechanical, reliability, manufacturing, and test considerations in parallel. No single workflow can manage 2.5D and 3D heterogeneous designs end to end.
Architectural planning, physical implementation, design analysis, reliability assessment, and test planning all need to happen through connected, multi-domain processes that support predictive modeling, in-design analysis, and final signoff.
Thermal management alone has grown dramatically more complex. The iNEMI Heterogeneous Integration Roadmap identifies three compounding drivers: the heterogeneity of heat generation within a single package, the increasing use of package-level thermal hardware, and the coupling of thermal management design with the electronics architecture itself. A 3D-stacked chiplet package does not have a single thermal profile—it has many, and they interact.
Mechanical and electrical considerations are similarly entangled. Through-silicon via (TSV) technology enables vertical chip-to-chip interconnection in 3D stacking, improving performance and power efficiency compared with traditional interconnect approaches. But those advantages depend on extremely precise manufacturing conditions, including surface flatness, cleanroom controls, and tightly managed bonding processes. As stack complexity increases, small process variations can have outsized effects on yield, reliability, and downstream qualification.
How does ECAD-MCAD collaboration need to evolve for advanced packaging?
For most electronics organizations, ECAD and MCAD have historically operated in separate lanes—electrical engineers own the schematic and layout; mechanical engineers own the physical enclosure. Advanced packaging erases that boundary. At the die, package, and substrate level, electrical performance, mechanical stress, and thermal behavior are inseparable design variables.
Coordinating across these domains requires active collaboration frameworks, not sequential handoffs. At the package-board boundary—where IC die, package substrate, and PCB interact—cross-discipline collaboration becomes both essential and challenging. This is particularly true for fan-out wafer-level packaging, where die shift, warpage, and process variation must be anticipated early and managed jointly by electrical, mechanical, and process engineers.
What new requirements does advanced packaging create for BOM and change management?
A traditional semiconductor BOM captures components and assembly relationships within a known structure. An advanced package BOM captures something considerably more complex.
Chiplet packages integrate dies from different design houses, foundries, and process nodes. Each chiplet carries its own qualification status, lifecycle stage, and supply chain dependencies. The interposer, substrate, die-attach materials, redistribution layers, and thermal interface materials each represent a separate design and sourcing domain. A change to any one of these elements—a substrate supplier change, a die revision, a process recipe update at the foundry—can propagate across the entire package in ways that a flat or simple BOM structure cannot track.
This is compounded by the absence of standardized nomenclature. There is a lack of a broadly accepted taxonomy for SiP architectures, which creates ambiguity in design handoffs, supplier communications, and lifecycle documentation. Without a shared vocabulary, even identifying what changed in a package revision becomes a non-trivial exercise.
For hybrid IDMs and fabless companies in particular—organizations that design their own products but outsource fabrication, packaging, and test to OSATs and foundries—this creates a multi-boundary change governance problem. A design change that originates in the silicon must be tracked as it affects the package specification, the substrate procurement, the OSAT process instructions, and the qualification records. Semiconductor companies typically use six or more disconnected systems to manage product data. Without a structured lifecycle management approach, that change propagation relies on manual coordination—a fragile dependency at multi-die complexity.
These dependencies become especially difficult after tapeout, when controlled product information must move from design into fabrication, packaging, test, and qualification.
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Read the BlogWhat does a modern lifecycle strategy for advanced packaging look like?
The iNEMI Roadmap frames the challenge precisely: challenges in heterogeneous integration "have to be addressed throughout the product lifecycle, from design to assembly to test," and a complex integrated system (CIS) approach is "the only way forward."
Translating that into practice means reframing the package not as a downstream deliverable but as a product-level entity that requires its own lifecycle governance. Several principles guide this reframing:
Treat the package BOM as a first-class product structure.
The packaging BOM—encompassing die, interposer, substrate, encapsulant, and thermal management materials—requires the same versioning, change governance, and traceability as any other product assembly. For advanced packages, this BOM can be as complex as a mechanical sub-assembly.
Establish cross-domain change governance.
When a revision in one domain (silicon design, packaging, test) has downstream impact in another, the change process must explicitly route through all affected domains. Engineering Change Orders (ECOs) that touch packaging must trigger review by electrical, mechanical, thermal, and reliability stakeholders before release.
Federate at the EDA boundary—don't replace it.
The IC design flow lives within EDA tools (Cadence, Synopsys, Siemens EDA) and operates in proprietary, tightly integrated ecosystems. Lifecycle management systems complement EDA by managing the product definition, BOM, specifications, qualification records, and change history that surround the design—not by attempting to manage the design data itself.
Build traceability from requirements through qualification.
For automotive (AEC-Q100, ISO 26262), aerospace, and medical applications, the traceability chain from customer requirements through design inputs, package specifications, and qualification results is non-negotiable. Establishing this chain from the start of the packaging program reduces rework and compliance risk at the end.
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Build AI-Ready DataAdvanced packaging is more than a design challenges, it’s a lifecycle problem
The shift to advanced packaging changes the competitive calculus for every semiconductor organization that touches the package—IDMs, fabless companies, and OSATs alike. Package architecture now determines product performance, power efficiency, time-to-market, and manufacturing yield. These are lifecycle outcomes, not just design outcomes.
Organizations that establish structured lifecycle management for their packaging programs—with governed BOM structures, cross-domain change processes, and clear traceability from design through qualification—will be better positioned to move faster, reduce respins, and coordinate effectively across the distributed ecosystem of foundries, substrate suppliers, and OSATs that advanced packaging depends on.
The package has become part of the product. Lifecycle management needs to follow.
Frequently Asked Questions
What is advanced packaging in semiconductors, and why does it matter for lifecycle management?
Advanced packaging refers to techniques—including chiplets, 2.5D silicon interposer integration, 3D stacking, and fan-out wafer-level packaging—that integrate multiple dies or functional blocks into a single package. Advanced packaging matters for lifecycle management because the package itself now defines product performance and architecture. Changes to the package ripple across die selection, substrate design, thermal management, and test procedures, requiring coordinated change governance across every affected domain.
How does chiplet-based design increase BOM complexity?
In a chiplet design, multiple dies from different foundries, process nodes, and design houses are integrated into a single package. Each chiplet has its own qualification status, lifecycle stage, and supply chain. The interposer, redistribution layers, substrates, and thermal interface materials add further layers to the BOM. A change to any one element can propagate across the entire structure—requiring a BOM architecture and change management process capable of tracking multi-level, multi-source dependencies.
What is the difference between ECAD-MCAD collaboration for traditional PCB design and for advanced packaging?
In traditional PCB design, ECAD and MCAD disciplines collaborate primarily at the board-enclosure interface. In advanced packaging, the boundary between electrical and mechanical design moves to the die-package-substrate level. Thermal coupling between stacked dies, mechanical stress from coefficient of thermal expansion (CTE) mismatches, and warpage in wafer-level packaging all require concurrent input from electrical, mechanical, and process engineers—well before a layout is finalized.
What role does PLM play in advanced packaging programs?
Product lifecycle management (PLM) systems support advanced packaging programs by providing structured BOM management for multi-component packages, engineering change governance that spans design, packaging, and test domains, and traceability from customer requirements through design specifications to qualification evidence. PLM does not replace EDA tools; it federates at the EDA boundary, managing the product definition and lifecycle records that surround the design flow.
Which semiconductor organizations face the most complex lifecycle management challenges for advanced packaging?
Hybrid IDMs—companies such as Analog Devices, NXP, Infineon, and STMicroelectronics that design their own products, operate some in-house fabrication, and outsource packaging and test to OSATs—face the broadest lifecycle management challenge. They must manage data handoffs, change governance, and quality traceability across both internal and external organizational boundaries simultaneously. Fabless companies that depend entirely on OSAT partners for advanced packaging face comparable coordination complexity.
A modern packaging strategy is one part of a broader goal: maintaining engineering continuity across internal teams, external manufacturers, and the full product lifecycle. For companies operating both owned fabs and outsourced production, that challenge becomes even more complex.
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